Publication
HOST 2014
Conference paper

Verification of untrusted chips using trusted layout and emission measurements

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Abstract

This paper presents a novel methodology for hardware security and Trojan detection applications. The method is based on our proposed tester-based optical methodology that combines different test patterns, time-integrated and time-resolved emission measurements to localize gates, detect logic states, and identify functional block activity inside a chip in a non-invasive fashion. A detailed application example using a 90 nm bulk digital test chip shows that emission images can be effectively used to identify unexpected and missing emission signatures that may be related to chip alterations. © 2014 IEEE.

Date

Publication

HOST 2014

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