Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell

Abstract

In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write stability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write stability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write stability. It is also shown that the use of high-Vt cell transistors can improve the read and write stability without causing significant performance degradation. © 2004 IEEE.