Variability analysis for sub-100nm PD/SOI sense-amplifier
Saibal Mukhopadhyay, Rajiv V. Joshi, et al.
ISQED 2008
This paper presents an on-chip characterization method for random variation in minimum sized devices in nanometer technologies, using a sense amplifier-based test circuit. Instead of analog current measurements required in conventional techniques, the presented circuit operates using digital voltage measurements. Simulations of the test structure using predictive 70 nm and hardware based 0.13 μm CMOS technologies show good accuracy (error ∼5%-10%) in the prediction of random variation even in the presence of systematic variations. A test chip is fabricated in 0.13 μm bulk CMOS technology and measured to demonstrate the operation of the test structure. © 2008 IEEE.
Saibal Mukhopadhyay, Rajiv V. Joshi, et al.
ISQED 2008
Stas Polonsky, Keith A. Jenkins, et al.
IEEE ITC 2004
Keith A. Jenkins, J.Y.-C. Sun, et al.
IEEE Transactions on Electron Devices
Keith A. Jenkins
IEEE T-ED