Conference paper
Sub-40nm V-groove MOSFETs
J. Appenzeller, R. Martel, et al.
DRC 2001
A planar, triple-self-aligned, double-gate GET process is implemented where a unique sidewall source/drain structure permits self-aligned patterning of the back-gate layer after the source/drain (S/D) structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. Moreover, double-gate FET (DGFET) operation is demonstrated with good transport at both interfaces.
J. Appenzeller, R. Martel, et al.
DRC 2001
C.T. Black, K.W. Guarini, et al.
Materials Research Society Symposium - Proceedings
A. Topol, D.C. La Tulipe, et al.
VMIC 2005
Jeffrey W. Sleight, Sarunya Bangsaruntip, et al.
DRC 2010