S. Shapira, U. Sivan, et al.
Physical Review Letters
A planar, triple-self-aligned, double-gate GET process is implemented where a unique sidewall source/drain structure permits self-aligned patterning of the back-gate layer after the source/drain (S/D) structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. Moreover, double-gate FET (DGFET) operation is demonstrated with good transport at both interfaces.
S. Shapira, U. Sivan, et al.
Physical Review Letters
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D.J. Frank, P. Solomon, et al.
LPED 1997
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Progress in Photovoltaics