Tunnel Current Measurements on P/N Junction Diodes and Implications for Future Device Design

Abstract

Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs., tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3×10 7 A/cm 2 at 300K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.