Temperature scaling of nanoscale silicon MOSFETs

Abstract

We have combined a 1D model of double-gate MOSFETs with ultrathin intrinsic channel, with a simple model of power consumption in digital integrated circuits, to calculate the temperature dependence of the minimum total (static + dynamic) power P and the optimal power supply voltage VDD. The results are strongly dependent on the circuit speed assumptions. If the current trend of speed scaling with the critical size reduction is sustained, both P and VDD saturate as soon as T is decreased below ∼ 100 K. On the other hand, if the high speed condition is removed, transistors may operate in the subthreshold region and minimum value of P scales as T2 while the optimum value of VDD drops as T. This reduction is, however, limited by thermal fluctuations, leading to a different scaling, VDD ∝ T1/2 and P ∝ T1, for low temperatures and/or large circuit densities. Because of this limitation, deep cooling of CMOS circuits may make sense only in very special cases.