Technique for producing highly planar Si/SiO_0.64Ge_0.36/Si metal-oxide-semiconductor field effect transistor channels

Abstract

Low temperature growth of Si/Si0.64Ge0.36/SiO2 heterostructures with high Ge content were found to have abrupt and planar interfaces after annealing at 800 °C. The improvement of transport characteristics with annealing was caused by the decreased in the grown-in point defects from the SiGe channel. The layers can endure 120 minutes of thermal oxidation at 800 °C which is typically required in deep submicron device fabrication. The microroughening of SiGe alloy can be suppressed by placing the SiO2/Si interface near to the SiGe channel so that the hole confinement in the SiGe and the device performance can be maximize.