The clock distribution of the power4 microprocessor
Phillip J. Restle, Craig A. Carter, et al.
ISSCC 2002
A tree-driven clock grid has become the choice of clock delivery for most microprocessors, due to its ability to achieve lower skew and lower variability than clock trees, and is becoming the choice of clock delivery for certain high-end application-specific integrated circuit designs. This paper reports on a clock routing tool that was used in designing multiple tree-driven clock grids in a 2.3 GHz processor system-on-chip, which achieved below 5 ps skew within 500 μm Manhattan distance and below 10 ps skew across each clock grid. This clock routing tool employs a nonsequential algorithm comprised of linear programming and combinatorial heuristics. Its robust length-matching capability enables flexible buffer placement, improved clock signal quality, and robustness to variations. © 2012 IEEE.
Phillip J. Restle, Craig A. Carter, et al.
ISSCC 2002
Nancy Y. Zhou, Phillip Restle, et al.
SLIP 2014
Steven C. Chan, Kenneth L. Shepard, et al.
ICCD 2003
Dieter F. Wendel, Ron Kalla, et al.
IEEE Journal of Solid-State Circuits