Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65NM bulk CMOS technologies

Abstract

We explore the effect of layout factors on the turn-on time of Silicon Controlled Rectifiers (SCRs) in 90nm and 65nm bulk CMOS technologies. Using a Very Fast Transmission Line Pulse (VFTLP) tester, we show that a SCR in 65nm bulk CMOS technology can achieve a turn-on time of 500ps with proper design. Using device simulations, we identify factors limiting SCR turn-on time and provide a basis for the presented experimental results. © 2006 IEEE.