Performance test case generation for microprocessors
Pradip Bose
VTS 1998
A general theory for characterizing and then realizing algorithms in hardware is given. The physical process of computation is interpreted in terms of a graph in physical space and time, and then an embedding into this graph of another graph which characterizes data flow in particular algorithms is given. The types of the special class of computational structures called systolic arrays which can occur physically are completely described, and a technique is developed for mapping the graph of a particular systolic algorithm into a physical array. Examples illustrate the methodology. © 1984 Springer-Verlag.
Pradip Bose
VTS 1998
Limin Hu
IEEE/ACM Transactions on Networking
S. Sattanathan, N.C. Narendra, et al.
CONTEXT 2005
Alfonso P. Cardenas, Larry F. Bowman, et al.
ACM Annual Conference 1975