Conference paper
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2005
A small-area digital-to-analogue converter (DAC) in 45nm SOI CMOS technology is presented that is based on a centrally located, static current-mode DAC, the output current of which is fed to an array of distributed, dynamically-refreshed small-area DACs. Owing to the dynamic operation of the distributed DACs, a single array element can be made as small as 8 × 8m. The measured retention time of a single array element with 7-bit resolution is 3ms at a temperature of 125°C. © 2010 The Institution of Engineering and Technology.
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2005
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ISSCC 2017
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RFIC 2004