Robin Hood: A system timing verifier for multi-phase level-sensitive clock designs

Abstract

An efficient system timing verification approach that employs latch graph representation is reported. It is a general approach that can handle most blocking schemes. Both early and late mode timing constraints are considered. The tool generates a detailed stack report to help designers identify where and how much the correction should be in case of violations. The algorithm has been implemented and tested on several real designs. An example with 1926 latches and dense interconnections is verified in 0.62 s.