Reliable Chiplet Integration on High Density Laminate (2.X D) for AI Hardware

Abstract

In this study, High Density Laminate with a bonded organic interposer (2.XD Laminate) is described and evaluated. The 2.XD laminate has <3 μm/3 μm L/S in the region of organic interposer. The test vehicle of three chip module is used to evaluate these laminates. Three chips include a High Bandwidth Memory (HBM2) test chip, a logic chip with dual pitch gC4s and an accelerator chip. The challenges associated with mix pitch and warpage due to organic interposer are explained.These High-Density Laminates are then tested with JEDEC standard reliability tests: High Temperature Storage (HTS), Temperature Humidity Bias (THB), Deep Thermal Cycling (DTC) and Accelerated Thermal Cycling (ATC) and extended thermal cycling up to 2000 cycles in DTC and 6000 cycles in ATC. The results are presented and discussed. A physical analysis is done on the parts after extended cycling which shows no sign of degradation. From design point of view stack vias configurations are also tested in reliability. The results obtained are then explained through Finite Element Model (FEM).