Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security

Abstract

This paper studies the impact of accelerated aging of a circuit containing a large variety of 14 nm scan chains using elevated voltage stress. Both IDDQ and timing performance changes are monitored to observe the aging of the circuit. Particular attention is dedicated to discussing the impact of the test pattern selection for both stress and sensing. The scan chain results are compared against previous results from 14 nm ring oscillators, confirming a good agreement. Simplified models are developed to explain the results and help understand the impact of aging on the circuit. In addition, the application to the hardware security is suggested given the measured aging signature.