Conference paper
Asymmetrical SRAM cells with enhanced read and write margins
Keunwoo Kim, Jae-Joon Kim, et al.
VLSI-TSA 2007
We propose an asymmetric-MOSFET-based sixtransistor (6T) SRAM cell to alleviate the conflicting requirements of read and write operations. The source-to-drain and drain-to-source characteristics of access transistors are optimized to improve writability without sacrificing read stability. The proposed technique improves the writability by 9%-11%, with iso read stability being compared with a conventional 6T SRAM cell based on symmetric-MOSFET access transistors in 45-nm technology. © 2009 IEEE.
Keunwoo Kim, Jae-Joon Kim, et al.
VLSI-TSA 2007
Rahul Rao, Keith A. Jenkins, et al.
IEEE Journal of Solid-State Circuits
Amlan Ghosh, Rahul M. Rao, et al.
IEEE Transactions on VLSI Systems
Jae-Joon Kim, Rahul Rao, et al.
CICC 2010