Record-performance In(Ga)As MOSFETs targeting ITRS high-performance and low-power logic

We review development of In(Ga)As-channel MOSFETs. InAs and InGaAs channels, combined with thin gate dielectrics, provide high transconductance, but off-state leakage can be high due to bandband tunneling currents. This leakage is reduced through thin 2.5-3nm channels, and through InGaAs or InP vertical field spacers in the raised source and drain. Devices with 2.7nm InAs channels and lightly-doped InGaAs source/drain spacers, at 25nm L, provide a record 0.5mA/μm I at 100nA/μm I and 500mV V. 1 μm L FETs show 61mV/decade subthreshold swing at V=0.1 V. Targeting the LP specification, we have developed InGaAschannel MOSFETs with lightly-doped InP wide-bandgap source/drain spacer layers. At 30nm gate length, these show a minimum 60 pA/μm I, approximately 100:1 smaller than a similar device using InGaAs source/drain spacers. A FET using InP spacers, with 45 nm gate length, shows 0.15 mA/μm I at 1nA/μm I and 500mV V.