Recent advances in search for suitable high-k/metal gate solutions to replace SiON/Poly-silicon gate stacks in CMOS devices for 45nm and beyond technologies

Abstract

The criterion for a suitable high-K dielectric/metal gate stack for replacing SiON/Poly-Si stacks in conventional CMOS devices are i) Equivalent oxide thickness (EOT) of ≤ 1.1 nm, ii) Electron and hole mobilities that are comparable to conventional stacks, and iii) Near Band-Edge (BE) threshold voltages for both nFET and pFET devices. Aggressive scaling and competitive mobilities have been demonstrated using HfO2/metal gate stacks [1] through optimization of interfacial layer composition, choice of suitable metal electrodes and deposition processes, and high thermal budgets that are compatible with conventional FET fabrication. A suitable NFET BE solution compatible with gate first process flow achieved by inserting capping layers containing gp. IIA (e.g., Mg) & gp. IIIB (e.g., La) elements into proven high mobility mid-gap HfO2/TiN gate stacks thereby moving the effective work function (EWF) to nFET BE [2,3]. On the pFET front, the challenge remains that elements with high bulk workfunction exhibit Vt instability as well as inherent scaling limitations after high temperature processing that is required in a gate first process flow. © The Electrochemical Society.