Process-design considerations for three dimensional memory integration

Abstract

3D integration of memory for both memory and processor caches provide a fertile application space for 3D integration. A simple 2 strata stack can reduce individual die size by approximately half, improving chip yield. Multi chip memory stacks can ease packaging and can significantly reduce power for main memory. Such stacks are easily testable and repairable through redundancy The design of such 3D stacks is critically dependent on the TSV technology used and is expected to become more attractive as TSV diameters and TSV overhead reduce.