Yang Yang, James Di Sarro, et al.
IRPS 2010
We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to hardware data correlation.
Yang Yang, James Di Sarro, et al.
IRPS 2010
Souvick Mitra, Ephrem Gebreselasie, et al.
EOS/ESD 2015
Junjun Li, Robert Gauthier, et al.
EOS/ESD 2006
James Di Sarro, Kiran Chatty, et al.
IRPS 2007