Gokul Krishnan, Li Yang, et al.
IEEE TC
This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.
Gokul Krishnan, Li Yang, et al.
IEEE TC
Keunwoo Kim, Hussein I. Hanafi, et al.
IEEE Transactions on Electron Devices
Keunwoo Kim, Rajiv V. Joshi, et al.
ISLPED 2003
Sumit Diware, Anteneh Gebregiorgis, et al.
AICAS 2021