Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical n+}/p+ polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented. © 2008 IEEE.
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
Karan Bhatia, Keunwoo Kim, et al.
IEEE SOI 2006
Saibal Mukhopadhyay, Keunwoo Kim, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Saibal Mukhopadhyay, Keunwoo Kim, et al.
IEEE Journal of Solid-State Circuits