High performance CMOS variability in the 65nm regime and beyond
Sani Nassif, Kerry Bernstein, et al.
IEDM 2007
Low-temperature characterization has been performed on fully depleted silicon-on-insulator (FDSOI) field-effect-transistor (FET) with gate length (Lg) down to 25 nm to clarify transport mechanisms that determine device performance in deca-nanometer scale. Linear drain current of FDSOI FET follows Lg-1 scaling down to 25 nm Lg, where mobility dominates, while saturation drain current largely deviates from L g-1 scaling. Temperature dependence of effective source velocity at high drain voltage (Vds) is weaker than that at low Vds in short Lg and is consistent with that of saturation velocity. Drift velocity measurement revealed velocity overshooting behavior at high lateral field, indicating further Lg scaling benefit. © 2011 American Institute of Physics.
Sani Nassif, Kerry Bernstein, et al.
IEDM 2007
Wan Sik Hwang, Amit Verma, et al.
Applied Physics Letters
Xinlin Wang, Andres Bryant, et al.
SISPAD 2007
Masaharu Kobayashi, Jérǒme Mitard, et al.
IEEE T-ED