R. Brayton, R. Willoughby
IEEE Transactions on Electronic Computers
A new approach for the minimization and optimization of multilevel logic circuits is described. Given any arbitrary multilevel representation of a block of combinatorial logic, the necessary and sufficient conditions of determining a minimal (i. e. prime and irredundant) representation of this logic block is developed. This is accomplished by extending the notions of prime and irredundant, previously used only for two-level logic minimization, to combinational multilevel logic circuits. An algorithm that produces a minimal multilevel representation of the logic from a multilevel representation of the circuit is presented. It is shown that prime and irredundant multilevel logic circuits are 100% testable for stuck faults, and that these tests are provided as a byproduct of the minimization.
R. Brayton, R. Willoughby
IEEE Transactions on Electronic Computers
Pradip Bose
ICCD 1985
R. Brayton, Norman Brenner, et al.
ISCAS 1984
J. Cullum, R. Brayton
Journal of Optimization Theory and Applications