Conference paper
Performance test case generation for microprocessors
Pradip Bose
VTS 1998
The problem of efficient generation of code to evaluate arithmetic expressions under varied assumptions of the underlying execution model is considered. A RISC-style load/store instruction set architecture is assumed throughout. Initially, a simple, nonpipelined, strictly serial execution model with N registers is considered. The machine model is then modified to allow pipelined execution of a single instruction stream. Finally, a decoupled access/execute model is considered in which each (decoupled) unit is pipelined.
Pradip Bose
VTS 1998
Raul Camposano, Arno Kunzmann
ICCD 1985
A.-T. Nguyen, J.-D. Wellman, et al.
HPCC 1997
Shauchi Ong, M.Y. Tsai, et al.
ICCD 1985