Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters

Abstract

The effect of oxide breakdown (BD) on the performance of several CMOS circuits has been investigated and a model for the oxide BD current-voltage (IV) characteristics has been experimentally verified on CMOS inverters. The results show that the inverter performance can be affected by the breakdown in a different way depending on the stress polarity applied to the inverter input. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains. In all the cases, the oxide breakdown conduction has been modeled as gate-to-diffusion leakage with a power law formula of the type I-KVP which was previously found to describe the breakdown in capacitor structures. This seems to indicate that the breakdown physics at oxide level is the same as at circuit level.