Model-to-hardware correlations in the design of a 50Gb/s package

Abstract

In the design course of a package for 50Gb/s SiGe BiCMOS 4:1 Multiplexer and 1:4 Demultiplexer, simulations of each individual section in the package were performed prior to the package design and followed by measurements to find model-to-hardware correlations to support future wideband high frequency applications. Sectional models were constructed and simulated using 3D full wave EM tools, and the results were cascaded to predict the performance of the entire package. Some test structures were also fabricated to help fine tune modeling schemes. Both S-parameter measurements and large signal operational tests were performed to examine the correlations with modeling results. The package was operated up to 56Gb/s, and the digital waveform degradation was correlated to S-parameter simulations and measurements with inverse Fourier transform. In General, the insertion loses from simulations match reasonably well with those from measurements while the reflections are lower especially at frequencies above 30GHz. This discrepancy also tends to affect precise predictions of waveform degradations.