Publication
IRPS 2004
Conference paper
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
Abstract
An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM's 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.