Publication
IEEE International SOI Conference 2001
Conference paper

Measurement of history effect in PD/SOI single-ended CPL circuit

Abstract

Direct measurement of history effect in partially depleted silicon on insulator (PD/SOI) was discussed. The mechanism of the history effect in complementary pass-transistor logic (CPL) circuit was also analyzed. The results showed that the relative history effect of CPL gates increases as the supply voltage is lowered.

Date

Publication

IEEE International SOI Conference 2001

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