Low-power-consuming 24-Gb/s multiplexer in 90-nm CMOS for optical transceivers

Abstract

In this paper, an integrated 2-to-1 selector multiplexer in 90-nm complementary metal-oxide semiconductor (CMOS) digital technology is presented. The multiplexer is based on a differential Gilbert-cell structure. Peaking inductors are used to improve the bandwidth. At a supply voltage of 1.2 V, a speed performance of 24 Gb/s is achieved. The circuit core consumes only 10 mA. Common drain output buffers allow measurements at 50 Ω. © 2004 IEEE.