Low-Frequency Noise in InGaAs-OI Transistors with 1T-DRAM Capabilities

Abstract

III-V compounds have recently attracted high expectation due to their potential to relieve the semiconductor scaling constraints. These materials present a high channel mobility and have demonstrated compatible integration with standard CMOS technology implementing 3-D processes. The capability to potentially incorporate memory functions in back-end-of-line (BEOL) layers while CMOS layers perform logic operations at front-end-of-line (FEOL) opens the door to increase the circuit performance at the same chip area. Scaled Indium gallium arsenide (InGaAs) transistors have recently proved to operate as single transistor DRAM exploiting the floating-body effect, enabling getting rid of the external capacitor and minimizing the cell footprint. However, extensive characterization of the interface quality and disturbing mechanisms affecting the device operation are still required. This work addresses the low frequency noise characterization of these III-V InGaAs transistors focusing on their DRAM operation. The experimentally extracted power spectral density of current follows a flicker-noise characteristic which points to carrier number fluctuations as the main noise source. However, mobility degradation associated to trapping-detrapping carrier phenomena has to be also taken into account to model the device operation. Finally, the device dimension and the back-gate bias dependence on the effective trap density have been evaluated.