Line edge roughness and spacing effect on low-k TDDB characteristics

Abstract

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously [1-3], there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced. ©2008 IEEE.