W.H. Henkels
Applied Physics Letters
A detailed optimized design of a 1 K-bit memory cell array with drivers and reset gates has been carried out based upon a set of projections for achievable tolerances in linewidths, resistances, and Josephson critical currents in a 2.5-μm technology employing niobium edge junctions. The cell operating regions were significantly widened relative to a predecessor Pb-alloy design by adjusting gate and cell inductances, adjusting current levels, and by employing a different timing sequence for application of write controls. Much-improved control of array-line current oscillations, without loss of speed, was achieved by employing a distributed filtering scheme using distributed damping. The design employs trimming of currents to accommodate ±8% chip-to-chip differences in the average critical current. The cell size is 63×63 μm. Monte Carlo calculations of threshold curve tolerances and operating current sensitivities and tolerances lead to a design-limited yield of about 95% for 4 K bits.
W.H. Henkels
Applied Physics Letters
W.H. Henkels, L.M. Geppert, et al.
Journal of Applied Physics
W.H. Henkels, L.M. Geppert, et al.
Journal of Applied Physics
W.H. Henkels, L.M. Geppert, et al.
Journal of Applied Physics