Conference paper
Analyzing path delays for accelerated testing of logic chips
Emily Ray, Barry P. Linder, et al.
IRPS 2015
The I/O interface latchup analysis using optical and electrical testing was discussed. JEDEC78 testing procedure, an automated computer-controlled latchup test program, was developed for the analysis. Emission of microscopy was used to characterize the ignition and diffusion of latchup in a series of I/O pins of a test chip. The results show that minority carriers can diffuse underneath lines of decoupling capacitances, if the recombination length of the minority carriers is comparable with the size of the capacitance.
Emily Ray, Barry P. Linder, et al.
IRPS 2015
Franco Stellari, Peilin Song
Microelectronics Reliability
Jing Li, Robert Montoye, et al.
VLSI Circuits 2013
Cyril Cabral, Robert B. Laibowitz, et al.
Microelectronic Engineering