Investigation of novel solder patterns for power delivery and heat removal support

Abstract

An innovative approach for electrical chip to substrate and chip to chip interconnects is proposed. The coexistence of solder balls and rails on a chip is discussed, supporting power delivery and heat removal for high-performance flip-chip-onboard and 3D stack applications. The concept enables further bandwidth and current density scaling at a high count of interconnects for signaling, but also at a high solder area fill factor for power delivery and heat removal. The rail-shaped solder joints are also compatible with the current floorplans of microprocessors with voltages arranged in lines. After reflow, solder rails compared to balls can result in a much larger maximal solder width relative to their pads. Therefore, a staggered array arrangement was proposed to minimize shorting risk. In addition, a solder height engineering strategy utilizing modulated pad shapes is discussed to yield equal solder heights for balls and rails present on the same device. However, improper rail design was found to lead to two instability types: 1) Balling and 2) Asymmetric Solder Accumulation. The first is the result of a solder height to width ratio of larger than approximately 0.6 considering long rail lines. The second occurs due to fabrication imperfections. The initial non-symmetric pad/solder shape can cause the accumulation of solder at one rail end (typically the end with the larger area) after reflow. The stability of Bow Tie Rails against Asymmetric Solder Accumulation was investigated to provide design rules for a robust rail design. Accordingly, a solder shape phase diagram indicating the parameters of the three identified phases is compiled. Experimental investigations of reflown solder shapes were complemented with numerical results using a surface energy minimization tool called Surface Evolver. A prediction quality of better than 9% was identified indicating the applicability of the tool to perform solder shape designs. The solver was also capable to predict the mentioned instabilities, rendering the tool even more valuable. Finally, a thermal interface resistance benchmark of ball and rail-like interconnects is performed in a bulk thermal tester. The rail interface with a solder fill factor of 57% yielded a 7 times reduced interface resistance. © 2013 IEEE.