Conference paper
VLIW - A case study of parallelism verification
Allon Adir, Yaron Arbetman, et al.
DAC 2005
We report on our experience with a new test generation language for processor verification. The verification of two superscalar multiprocessors is described and we show the ease of expressing complex verification tasks. The cost and benefit are demonstrated: training takes up to six months; the simulation time required for a desired level of coverage has decreased by a factor of twenty; the number of escape bugs has been reduced.
Allon Adir, Yaron Arbetman, et al.
DAC 2005
Joachim Clabes, Joshua Friedrich, et al.
DAC 2004
Juan Antonio Carballo, Kevin Nowka, et al.
DAC 2004
Puneet Gupta, Fook-Luen Heng
DAC 2004