Measurement of high-speed ADCs
Lukas Kull, Danny Luu
CICC 2017
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32 × and 64 × interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64 × interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32 × interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32 × and 64 × interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology.
Lukas Kull, Danny Luu
CICC 2017
Lukas Kull, Danny Luu, et al.
VLSI Circuits 2018
Thomas Toifl, Christian Menolfi, et al.
IEEE Journal of Solid-State Circuits
Ronny Henker, J. Pliva, et al.
SPIE Optics + Photonics 2015