Hot carrier effect in ultra-scaled replacement metal gate Si_i-xGe_x channel p-FinFETs

Abstract

Hot carrier reliability is studied in replacement metal gate (RMG) Si1-xGex (x = 20%) channel p-FinFETs with high-k gate dielectrics. In this study, we show that: (1) interface state generation and hole-trapping contribute to the HC damage under high-Vg (∼Vd) stress conditions; (2) hot electron injection is the dominant degradation mechanism for low- and mid-Vg biases, which are more representative stress conditions during typical CMOS logic circuit operation. We also found that excessive electron trapping in ultra-scaled SiGe pFinFETs can reduce the effective channel length and significantly increase the off-state leakage current (Ioff).