Hardware Algorithm Co-optimization on Resistive RAM Cross-bar Array for Scalable Analog Compute Technology for AI application

Abstract

We optimize the hardware process for building a resistive RAM (RRAM) stack to increase the switching resistance while reducing the forming voltage (Vform), which are important ingredients for scalable analog computing. With increased resistance, we identified few immediate challenges. We demonstrate that one of those challenges, non-idealities in switching character, can be addressed by algorithm optimization.