Flip-flop upsets from single-event-transients in 65 nm clock circuits

This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and compared to upset rates measured on a 65 nm test chip with 15 MeV carbon ions and 148 MeV protons. © 2009 IEEE.