Publication
EPEPS 2012
Conference paper

Findings and considerations for I/O clock jitter on a source synchronous front side bus

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Abstract

This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts. © 2012 IEEE.

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Publication

EPEPS 2012

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