Fabrication of Tungsten Local Interconnect for VLSI Bipolar Technology

Abstract

We have developed a process for fabricating thin W films for local interconnect applications in circuits using Si bipolar transistors. Tungsten films deposited by both sputtering and chemical vapor deposition (CVD) methods were patterned over topography with a highly anisotropic and selective single-wafer reactive ion etch (RIE) process in Cl2 and O2. Maze structures were tested electrically to characterize the opens and shorts yield. In addition, the profiles of etched lines were characterized by cross-sectional scanning electron microscopy. High yields (>80%) were obtained for a wide range of RIE conditions on mazes of variable pitch (minimum 1.8 mm) with lengths >0.5 m. Yields were further increased using a simple “semi-planarization” of the underlying substrate prior to metal deposition. With a composite sputtered and CVD W bilayer (total thickness 350 nm), a local interconnect sheet resistance of <0.5 W/ was obtained with minimal topography added to the overall device structure. As a technological demonstration, device characteristics of a submicron bipolar circuit fabricated with sputtered tungsten local interconnect were measured. Near ideal Gummel characteristics were obtained, and emitter-coupled-logic ring oscillator gate delays of 38 ps were measured at a switch current density of 0.6 mA/μm2. © 1993, The Electrochemical Society, Inc. All rights reserved.