External Resistance Reduction by Nanosecond Laser Anneal in Si/SiGe CMOS Technology

Abstract

We report on a significant pFET external resistance reduction (∼40%) and corresponding 10% R ON decrease by nanosecond laser annealing of S/D structures applicable to advanced technology nodes. Selective melting of pFET S/D elements is responsible for this improvement. Process window boundaries are defined by channel and junction melting at the upper end and by S/D SiGe melting at the lower end. Short channel characteristics are not degraded within the identified process window. Contacted gate pitch (CPP) and fin number dependence of the process window is assessed.