Zhigang Hu, Alper Buyuktosunoglu, et al.
ISLPED 2004
Larger cache sizes closer to processor cores increase processing efficiency, but physical limitations restrict cache sizes. Effective cache capacity can be expanded via the inline compression of data as it enters a lower level cache. Using the IBM Telum® L2 as a comparative baseline, this paper presents a custom compression scheme designed for small, line-sized data blocks, explores optimal compressor/decompressor placement, solutions to common compression drawbacks and proposes a tiered design blueprint to facilitate product integration. The impact of compression and prediction-assisted adaptive compression on effective cache capacity, hit rate and access latency across several typical industry workloads is explored.
Zhigang Hu, Alper Buyuktosunoglu, et al.
ISLPED 2004
Ilias Iliadis
International Journal On Advances In Networks And Services
Haoran Qiu, Weichao Mao, et al.
ASPLOS 2024
Hazar Yueksel, Ramon Bertran, et al.
MLSys 2020