Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication

Abstract

A scheme for building three-dimensional integrated circuits (ICs) based on the layer transfer of completed devices was presented. The processes required for stacking active device layers that preserve the intrinsic electrical characteristics of short-channel MOSFETs were analyzed. The impact of 3D IC fabrication processes on the performance and yield of intrinsic devices, ring oscillator, and interconnects was evaluated.