E. Babich, J. Paraszczak, et al.
Microelectronic Engineering
The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency without excessive computation times. Copyright © 1973 by The Institute of Electrical and Electronics Engineers, Inc.
E. Babich, J. Paraszczak, et al.
Microelectronic Engineering
Heinz Schmid, Hans Biebuyck, et al.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
K.N. Tu
Materials Science and Engineering: A
Daniel J. Coady, Amanda C. Engler, et al.
ACS Macro Letters