Revanth Kodoru, Atanu Saha, et al.
arXiv
The design and packaging of integrated circuits requires the calculation of capacitances for three-dimensional conductors located on parallel planes. An integral-equation (IE) computer-solution technique is presented, which provides accurate results. The solution technique minimizes computer storage requirements while maintaining calculating efficiency without excessive computation times. Copyright © 1973 by The Institute of Electrical and Electronics Engineers, Inc.
Revanth Kodoru, Atanu Saha, et al.
arXiv
Corneliu Constantinescu
SPIE Optical Engineering + Applications 2009
P. Alnot, D.J. Auerbach, et al.
Surface Science
Sang-Min Park, Mark P. Stoykovich, et al.
Advanced Materials