Abstract
In this correspondence we consider a model for dynamic memories that are characterized by small cell fan-out and a small number of I/O ports. Many schemes have been proposed in the literature to interconnect dynamic memory cells. These usually exhibit a tradeoff between random and block access times. We propose a scheme that combines the interconnection scheme of a previous work with the idea of interleaving. With this we show that both random and block access times can be optimized. We analyze access times for our scheme and compare them to those for other schemes in the literature. We define delay between two block accesses and compare the dynamic memory organization schemes on the basis of delay. © 1984 IEEE