Doping challenges in exploratory devices for high performance logic

Abstract

This paper presents an outlook for doping processes in high performance logic as new device structures and materials are introduced with the hope of continuing CMOS device performance improvements into the 10-20 nm channel length regime. Materials and structures that are considered interesting in this scaling work are strained silicon and strained silicon grown on silicon germanium, ultra thin silicon on insulator (SOI) materials, high-k dielectrics and metal gates, and double gated MOSFETs. Ramifications of using these materials on implant and doping technologies will be discussed.