Design Optimization of ASIC Designs via AI-driven RTL-to-GDS Optimization with Floorplanning

Using an Intelligent Chip Explorer, we leverage massive, cloud-enabled distributed computing and AI-driven optimization to enhance parameter tuning for EDA tools. As modern ASIC SoC designs grow more complex and integrate more third-party IPs, macro placement during chip designers becomes increasingly challenging. The thousands of parameters in EDA tools further complicate decision-making for chip designers. We first show steps to optimize power, performance, and area (PPA) using AI-driven cloud-compatible parameter tuning based on a fixed floorplan. Building on this, we demonstrate how AI-driven floorplanning optimization (FP-OPT), which adjusts the floorplan size and performs concurrent macro placement, can further improve the PPA. The optimized floorplan is then reintegrated into the initial optimization process, delivering even better results.