Design of IP media accelerator

Abstract

Multimedia processing is computation intensive and not efficient to be proceeded on current GPP (general purpose processor) based server architectures. In order to enhance the multimedia processing capability of servers, we propose a reconfigurable multi-core platform for media and network acceleration. The platform is composed of DSP array and FPGAs, and is compatible to IBM blade server specification. In this paper, we highlight the design challenge and present the hardware and software design of this accelerator. The prototype of IP Media Server (IMS) is implemented on this platform, which completes the essential functions of voice conference application. The first-stage test results are presented and the perspective of future work is proposed. © 2007 IEEE.