G. Almasi, G. Almasi, et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Short, medium and long on-chip interconnections having line widths of 0.7 - 52 μm are being analyzed in five-metal-layer structures. Design guidelines are formulated for local and global wiring in order to achieve minimum delay and contain crosstalk. The regime when inductive effects are significant is explained and the importance of resistive losses in the power buses is highlighted.
G. Almasi, G. Almasi, et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A. Deutsch, G. Arjavalingam, et al.
ECTC 1994
I.M. Elfadel, A. Deutsch, et al.
DATE 2004
P. Restle, Keith A. Jenkins, et al.
IEEE Journal of Solid-State Circuits